TIG torch PCBA kicked off in Adom AI....

Plenty of distractions at the moment - this year's Xmas cake, Xmas puddie and stollen weren't going to bake themselves. And the Samsung dual oven is now a month past its 5 year warranty, so losing control of the temperature was rather concerning and cost me my Xmas cake, so needed fixing. It appears to be an intermittent issue (it resolved itself before I could reach for the tools), so will need to be kept an eye on - or in my case a thermocouple and process controller (aka display).

With that now behind for the moment and without any more messing about, let's get started.

And we're off....

Let's see what he/she/it comes up with.

Various Claude questions:

I've built the edge fingers in KiCad on your DXF outline. Please check the drawing above before I start placement.

• Drawing: C:\Users\murra\adom-lib\tig-psr\outline-fingers.png
• KiCad preview board: ...\tig-psr\kicad\outline-preview.kicad_pcb

Fingers as built:

• Count, pitch and width: 5 fingers at 2.0 mm pitch, 1.3 mm wide, leaving 0.7 mm gaps.
• Length: 6.2 mm, from 0.3 mm in from the board edge to 0.5 mm short of the step out to the full 20.5 mm body.
• Edge clearances: 0.3 mm to the mating edge (JLCPCB's copper-to-routed-edge minimum). The outer fingers sit 0.35 mm from the tab's sides.
• Finish: HASL, solder mask open over the fingers, no solder paste.

Please confirm:

1. Finger length: I assumed 6.2 mm, filling the tab, since you didn't give a length. Is that right?
2. Sides: fingers on the top only? Copies on the bottom would contact either face of the socket, but they add bottom-side copper.
3. Pin order: the question marks in the drawing are my provisional order, 1 = +5V through 5 = GND, counting from the top as you look at the component side. What order does the welder's socket use?
4. Relay: TLP172A PhotoMOS (my recommendation), SIP-1A05 reed, or keep the HFD4/3? The board is small (772 mm²), so the 4 × 7 mm SMD PhotoMOS helps the fit a lot.
5. PSR: where does the sensor's tail land, at what pin spacing, and on which edge? Its two crimped pins look like about 2.5 mm pitch.
6. Corners: square as drawn, or rounded?

• The TLP172A opto SSR sounds like a reasonable suggestion. I know from my measurements and partial reverse engineering that the current and voltage needed to control the welder are very low. It's not actuating a remote relay inside the machine - at least not on mine.
• The PSR will be off-board, connected via 2 through holes, with pitch shown in the datasheet provided. I will incorporate it into the plastic  cover component. NB: Omit it from the sourcing BOM.
• Rounded PCB corners would be fine.
• NB: the fingers make contact on the "bottom" side of the PCBA but might as well use both sides.
• HASL will be fine for the fingers. Proper gold plating is not needed and even ENIG (basically anti-tarnish, nothing more) is unnecessary and would cost extra.

I'm going to need a 3D model of the final PCBA so that I can create the cover that will close the torch handle when this is fitted. For this I'm going to have to recreate the current torch handle in Fusion. And while the near-clone I acquired from Ali Express is very similar, the 2 control assemblies are not quite interchangeable so I will have to fiddle about with the final design so that it is compatible with both handles. At least the PCBs are almost identical in outline ie interchangeable (that's A Good Thing).

Here's a first cut of the schematic:

Doesn't look too silly. As before, the "reference" voltage is taken from the supply, as there's no deadly accuracy required and ultimately it's a ratiometric controller - most are simply potentiometers. Lots of HF and low pass filtering, which is good. I expect the expensive compts will be the SSR and the quad opamp, possibly the mini pots.

• The TLV9104 opamps are normally around £1 each, as these are low power, rail-to-rail devices. 
• The TLP172A opto SSRs are also around £1 each
• The Bourns pots are around £1.50 each
• ...doubtless I've missed something really expensive?

Top side copper and courtyard:

Bottom side copper (no compts fitted there):

The silk screen is a mess but there hasn't been any attempt to clean it up yet

And the 3D PCB view (with the silk screen turned off!). The SSR doesn't yet have a 3D footprint, so is missing (top left):

It's coming along. Claude says:

The schematic, the PCB editor and the 3D viewer are all open in KiCad on your PC. The project is in C:\Users\murra\adom-lib\tig-psr\kicad\.

This is a work-in-progress layout and is not ready to fabricate yet:

• Routing: every signal is connected and the board is clean against JLCPCB's 2-layer rules apart from silkscreen. KiCad's status bar shows 5 unrouted items, all ground. Bottom-side tracks split the GND plane into a few islands that the stitching vias don't yet join. Fixing that is next, by keeping more signals off the bottom layer.
• Silkscreen: not done yet. The value text overlapping parts and the edge in the 2D view will be cleaned up to JLCPCB minimums, with reference designators only.
• 3D: U2 (the TLP172A) shows no body because its footprint has no 3D model. I'll fix that.

Changes since rev C (I'll send you a revised schematic PDF with the layout):

• 0402 passives: most resistors and small capacitors are now 0402, all JLCPCB Basic parts. 0603 didn't fit the 42 × 20.5 mm board, which held 53 of the 72 parts.
  • Values changed to match what's stocked: the difference amp is 22 k / 47 k with 220 nF (gain 2.14 and a 15 Hz pole, trimmed out by RV1), hysteresis is 22 k / 1 M, and the excitation divider is 47 k / 12 k.
• Fingers: double-sided per your note, with each top/bottom pair joined by a plated hole at the inner end. The GND pour is kept off the finger tab.
• Test pads: 10 dedicated 0.8 mm pads for GND, +5V, VREF, VM, PSR, V1, AMP_OUT, VTH, CMP_OUT and SSR_K. Every other net can be probed at an exposed top-side component pad, which your "bare track / test point" note allows.
• Indicator LED: now driven from the comparator output through 470 Ω. That freed routing space next to the PhotoMOS.
• Net names: DRAIN, GATE and VOUT_INT are now SSR_K, Q1_G and AMP_OUT. AI Flow's router treats nets named like MOSFET or power nets differently, and its saved plans had been dropping DRAIN and VOUT_INT.

The layout follows your concept: fingers on the left, the PhotoMOS by fingers 1–2, supply input by fingers 4–5, the op-amp in the middle, both trimmers and the PSR pads at the narrow end.

Next steps?

The next steps, in order:

1. Ground plane. Fix the five unrouted GND items by keeping signals off the bottom layer, so the bottom stays an almost unbroken plane, which matters near the arc. Then 0 unrouted and a clean DRC against the JLCPCB rules.
2. Layout review. Check the key loops by eye: the sensor input path to U1, op-amp decoupling, the supply filter at fingers 4–5, and keeping the enable traces and their filter away from the analogue nets.
3. 3D models. Add the missing PhotoMOS (U2) body and check every part sits correctly in KiCad's 3D view.
4. Silkscreen. Top side only, at JLCPCB's minimum text size: reference designators, trimmer labels (SENS / THRESH with a direction arrow), finger names, test-pad names, and a board title.
5. Schematic and BOM refresh. A new schematic PDF with the 0402 values, a test-point map, and a BOM rechecked against live LCSC stock.
6. Simulation. A quick SPICE check of the analogue chain on the final values: linearity, threshold, hysteresis, and the 4.5–5.5 V supply range.
7. Manufacturing files.
   • Gerbers and drill files.
   • The JLCPCB BOM and pick-and-place file, with each part's rotation checked against JLCPCB's footprints. The PSR, edge fingers and test pads stay out of both files.
   • A final DRC on the exported set.
8. Your review. You get the board in KiCad plus a summary before anything goes to JLCPCB. I'd also run their online DFM check and placement preview, but uploading and ordering need your JLCPCB login and your go-ahead.

I'll start on the ground plane now unless you want to change anything first.

And within 10 mins or so, those final actions have been completed, resulting in this update. Silk screen tidied up, SSR 3D model showing:

I've run out of tokens for now. It rests in 2 hours, so just time to eat....